The present invention relates to a noise analysis model and a noise analysis method and, particularly, to a noise analysis model and a noise analysis method for noise that propagates through a substrate.
A semiconductor device that is incorporated into electronic equipment or the like is subject to noise due to the environment or the effect of another element on a circuit substrate of the semiconductor device. The noise propagates through the substrate of the semiconductor device and causes elements such as transistors formed on the substrate to malfunction. Thus, in order for the semiconductor device to operate normally, it is required to eliminate the effect of noise in the semiconductor device.
Therefore, when designing a semiconductor device, it is necessary to estimate the effect of noise at the design phase and make a circuit layout in consideration of the effect of noise. For this reason, noise analysis is performed at the design phase of a semiconductor device.
A technique to analyze substrate noise that propagates through a substrate of a semiconductor device has been proposed (Japanese Unexamined Patent Application Publication No. 2006-100718). In this technique, the substrate coupling network and the ground line network of the silicon chip are represented by the resistor mesh equivalent circuit. Then, the noise propagation characteristics of the silicon substrate from a circuit that generates noise to a circuit that has noise sensitivity are analyzed by circuit simulation. Further, the circuit that generates noise is analyzed separately by circuit simulation to thereby obtain the amount of generated noise. By integrating those separate element analyses, chip-level noise analysis is realized.